This invention relates to computer systems. More particularly, this invention relates to computer systems having configuration storage.
A computer system typically includes a processor, a memory, and a plurality of peripheral devices. These peripheral devices include, for example, keyboards, mice, display monitors, storage devices such as hard disk drives and compact-disk read-only-memories (CD-ROMs), printers, video cards, audio cards, modems, small computer system interfaces (SCSIs), universal serial buses (USBs), memory controllers, and other chips or chipsets. These peripheral devices are typically connected to one or more buses that allow the peripheral devices to interface with the system processor and memory to perform certain functions.
A computer system typically employs at least one bus system architecture for interfacing the peripheral devices with the system processor and memory. Such bus system architectures include, for example, the Industry Standard Architecture (ISA), Extended ISA (EISA), and Peripheral Component Interconnect (PCI) architecture. ISA and EISA are older bus architectures that handle less data bits at a slower clock speed than the PCI architecture. For example, ISA can handle 16-bit data transfers at a clock speed of 8 Megahertz (MHz). EISA can handle 32-bit data transfers at a clock speed of 8 MHz. PCI, however, can handle 32-bit or 64-bit data transfers at a clock speed of 33 MHz.
In particular, the PCI architecture specifies a PCI local bus that connects the processor, memory, and PCI compatible devices to a wider and faster data pathway. The PCI devices that interface with the PCI local bus include a variety of chips or chipsets that perform specialized functions. PCI devices include, for example, modems, video cards, audio cards, SCSIs, Northbridge devices, PCI-to-PCI bridges, USBs, memory controllers, and Local Area Network (LAN) adapters. These PCI devices can be integrated onto the main circuit board of the computer or can be added as expansion cards that fit into PCI slots connected to the PCI bus. A PCI bus can typically support three to five PCI devices.
Each PCI device includes its own configuration information. In addition to PCI devices, other devices in a computer system also include their own configuration information including, for example, devices compatible with other bus architectures (e.g., ISA, EISA), a memory-mapped input-output (I/O) space, and any addressable register block (e.g., central processing unit registers). This configuration information is typically provided in a centralized configuration storage that includes one or more address spaces, with each address space having a suitable number of bytes of addressable memory organized as configuration registers. For example, each address space in a PCI device includes 256 bytes of addressable memory organized as configuration registers. The configuration registers provide a computer system with information about the device and allow the device to be configured for use in a specific system.
Each device typically includes one or more design sections that use configuration storage to perform different functions, and in many instances, to interface with other components in the computer system.
Configuration storage, which is accessed by a host interface on the device, is typically organized as a single design entity located in close physical proximity is to the host interface. Data stored in configuration storage are then communicated to individual design sections that may be a considerable distance from the host interface. Global routing resources are then needed to route each configuration bit to the design section in which they are used, resulting in excessive routing resources. For example, a configuration bus containing a collection of signal wires (e.g., often hundreds or thousands) can be used to transfer a configuration bit from the centralized configuration storage to each design section. This can cause layout and timing problems in programmable logic device (PLD) designs, application-specific integrated circuit (ASIC) designs, and field-programmable gate array (FPGA) designs.
The design of a device typically includes the creation of a functional model using a hardware description language (HDL) such as Very High Speed Integrated Circuit Hardware Description Language (VHDL) or Verilog. The HDL code represents hardware information of the device (e.g., registers, control logic), which can then be compiled into a gate level-description that describes the device in terms of logic gates (e.g., AND gates, OR gates, exclusive OR (XOR) gates, inverters) and interconnections. This gate-level description can then be imported into a place-and-route tool that generates a netlist describing the electrical connectivity data associated with the device. The place-and-route process, also referred to as layout, represents the physical location of each transistor that makes up a logic gate and the interconnections between each logic gate on a semiconductor chip. The netlist data can then be used to drive fabrication of the device on the chip.
With current technologies that create devices using HDL, configuration storage is created manually. Because configuration registers are each customizable to one of several different classifications of registers, known methods require a user to manually describe each register in HDL code in order to customize those registers. This can be a laborious process that can lead to logic design errors in interpreting the configuration register specifications. Also, configuration registers not used in a device can have unconnected inputs and outputs that can lead to problems with place-and-route tools. Furthermore, test code for simulating test patterns in configuration storage is also manually created, thus also prone to errors.
In view of the foregoing, it would be desirable to improve the layout efficiency and logic design accuracy of providing configuration storage in devices.